The present disclosure relates to an adaptive receiver system configured to receive a reception signal and an adaptive transceiver system including the adaptive receiver system.
Japanese Patent Publication No. 2008-022537 discloses a receiver including an equalizer configured to receive a digital signal from a transmitter to change a frequency response of the digital signal, and a receiver logic configured to adjust a gain of the equalizer. In the receiver, the receiver logic samples output of the equalizer at a certain data point to generate a data value, and samples output of the equalizer at a certain boundary point of data to generate a boundary value. Then, the receiver logic adjusts the gain of the equalizer based on the generated data value and the generated boundary value.
Japanese Patent Publication No. 2008-099017 discloses a clock data recovery device configured to recover a clock signal based on an input digital signal. The clock data recovery device includes an equalizer, a sampler, a clock generator, and an equalizer controller. The equalizer is configured to adjust the level of an input digital signal and output the adjusted digital signal. The sampler is configured to sample a digital signal output from the equalizer by using a clock CKX representing data bit transition timing to obtain a value DX(n) and to sample a digital signal output from the equalizer by using a clock CK representing a central time of each bit duration to obtain a value D(n). The clock generator is configured to adjust, referring to FIG. 2 of Japanese Patent Publication No. 2008-099017, the phases of the clock CKX and the clock CK based on an UP signal (phase comparison signal) representing a significance value when “D(n−1)≠DX(n−1)=D(n)” is satisfied and a DN signal (phase comparison signal) representing the significance value when “D(n−1)=DX(n−1)≠D(n)” is satisfied. The equalizer controller is configured to control, based on the value D(n) and the value DX(n), an offset voltage value added to an input digital signal by the equalizer.
Japanese Patent Publication No. 2004-180188 discloses a clock data recovery circuit configured to compare the phases of input data and a sampling clock to generate a sampling clock based on a comparison result. In the clock data recovery circuit, the phase of the sampling clock is changed such that an edge of the sampling clock and an edge of the input data are apart from each other with more than a predetermined distance.